monday, mar 31, 2008 2:51 pm / 10-bit current output d to a converter DAC100 asd0011162 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2008 analog devices, inc. all rights reserved. 1.0 scope this specification documents the detail requ irements for space qualifi ed product manufactured on analog devices, inc.'s qml certified line per mil- prf-38535 level v except as modified herein. the manufacturing flow described in the standard space level products program brochure is to be considered a part of this specification. this brochure can be found at: http://www.analog.com/aerospace this data sheet specifically details the space grade version of this product. a more detailed operational description and a complete data shee t for commercial product grades can be found at www.analog.com/DAC100 2.0 part number . the complete part number(s) of this specification follow: part number description DAC100-703q 10-bit current output d to a converter DAC100-713q radiation tested, 10-bit current output d to a converter 2.1 case outline . letter descriptive designator case outline (lead finish per mil-prf-38535) q gdip1-t16 16-lead ceramic dual-in-line package (cerdip) 1 2 3 4 top view 8 7 6 5 9 10 14 11 13 12 16 15 r s full scale adjust v+ msb bit 2 bit 3 bit 4 bit 5 r b v- output lsb bit 9 bit 8 bit 7 bit 6 figure 1 - terminal connections .
DAC100 asd0011162 rev. f | page 2 of 5 vref r b = 6.12k ? r s * rb rs full scale adjust v- v+ analog output 16 1 13 6 7 8 9 10 11 12 4 5 msb lsb r s = 4.88k ? figure 1a: simplified schematic 3.0 absolute maximum ratings . (ta = 25c, unless otherwise noted) v+ supply to v- supply........................................................................................ 0v to 36v v+ supply to output............................................................................................ 0v to +18v v- supply to output............................................................................................. 0v to ?18v power dissipation ......................................................................................................500mw logic inputs to outputs........................................................................................-1v to +6v operating temperature range......................................................................-55c to +125c storage temperature range..........................................................................-65c to +150c lead temperature (soldering, 60 sec.) .......................................................................+300c dice junction temperature (t j )...................................................................................+175c 3.1 thermal characteristics : thermal resistance, cerdip (q) package junction-to-case ( jc ) = 29c/w max junction-to-ambient ( ja ) = 91 c/w max thermal resistance, flatpak (n) package junction-to-case ( jc ) = 22c/w max junction-to-ambient ( ja ) = 90 c/w max
DAC100 asd0011162 rev. f | page 3 of 5 4.0 electrical table : see notes at end of table table i parameter symbol conditions 1 / sub- group limit min limit max units power supply current i+ v ih = 2.1v 1, 2, 3 8.33 ma i- v ih = 2.1v 1, 2, 3 8.33 full range output voltage v fr v il = 0.7v, full adjust pin tied to v- 1, 2, 3 10.0 11.1 v zero scale output voltage v zs v ih = 2.1v 1, 2, 3 .013 %fs integral nonlinearity nl ? lsb ? 9 bits 1, 2, 3 0.1 full scale temperature coefficient tcv fr v il = 0.7v, full scale adjust pin tied to v- 8 60 ppm/ c logic inputs high v ih v in = 2.1v to 3v (all inputs) measured with respect to output pin allowing ? lsb change with ? v in 1, 2, 3 2.1 v logic inputs low v il v in = 0.7v to 0v (all inputs) measured with respect to output pin allowing ? lsb change with ? v in 1, 2, 3 0.7 logic input current high i ih v ih = 6.0v, each input 1, 2, 3 5 a logic input current low i il v il = 0v, each input 1, 2, 3 5 power supply sensitivity pss v il = 0.7v (all inputs) v s = 6v to 18v 1, 2, 3 0.1 %/v monotonicity 2 / ? i o measured at each major carry code point 1 0 a settling time 3 / t shl r l = 1k ? , c l 10pf 9 375 ns table i notes: 1/ v s = 15v, unless otherwise specified. 2/ the change in output current eith er increases or remains the same for an increasi ng digital input code. 3/ output within ? lsb of 10-bit accur acy final settled nominal value of v out . input pulse characteristics: input frequency = 1mhz squa re wave, 50% duty cycle. input amplitude = 0v to 2.1v input signal = t r , t f 20 ns measurement referenced to input high-to-low transition. dut settling time to 0.05 % fs
DAC100 asd0011162 rev. f | page 4 of 5 4.1 electrical test requirements : 1/ pda applies to subgroup 1. deltas not included in pda 2/ see table iii for deltas. see table i for test conditions. 4.2 table iii. burn-in test delta limits . table iii test burn-in lifetest delta title endpoint endp oint limit units v fr 10.55 0.55 10.55 0.75 0.2 v v zs 0.013 0.018 0.005 %fs i+ 8.33 8.33 10% ma i- 8.33 8.33 10% ma 5.0 life test/burn-in circuit: 5.1 htrb is not applicable for this drawing. 5.2 burn-in is per mil-std-883 method 1015 test condition b. 5.3 steady state life test is per mil-std-883 method 1005. table ii mil-std-883 test requirements subgroups (see table i) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1, 2, 3, 8 1/ 2/ group a test requirements 1, 2, 3, 8, 9 group c test requirements 1 2/ group d test requirements 1 * pda applies to subgroup 1 only. no other subgroups are included in pda.
DAC100 asd0011162 rev. f | page 5 of 5 rev description of change date a initiate 30-jun-00 b update web address feb. 18, 2002 c update web address. add group c and d to table ii. add life test endpoint based on delta to table iii. feb. 28, 2003 d delete burn-in circuit aug. 5, 2003 e update header/footer & add to 1.0 scope description feb. 21,2008 f remove minimum dice junction temp. range in 3.0 absolute max. ratings march 31, 2008 ? 2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective companies. printed in the u.s.a. 03/08
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